Split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells. The memory cell is shown in FIG. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 (also referred to a word line gate or select gate) has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22b that extends up and over the floating gate 20. The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling.
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
The memory cell is read by placing positive read voltages on the drain 16 and control gate 22 (which turns on the channel region under the control gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the drain 16), then the portion of the channel region under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
The architecture of the memory array is shown in FIG. 2. The memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end to end in mirror fashion, so that they are formed as pairs of memory cells each sharing a common source region 14 (S), and each adjacent set of memory cell pairs sharing a common drain region 16 (D). All the source regions 14 (S) for any given row of memory cells are electrically connected together by a source line 14a. Optionally, a group of the source lines 14a, or all the source lines 14a in the memory array, can be electrically connected together by a common source line 14b. All the drain regions 16 (D) for any given column of memory cells are electrically connected together by a bit line 16a. All the control gates 22 for any given row of memory cells are electrically connected together by a control gate line 22a (also called word lines or select gate lines). Therefore, while the memory cells can be individually programmed and read, memory cell erasure is performed row by row (each row of memory cells is erased together, by the application of a high voltage on the control gate line 22a). If a particular memory cell is to be erased, all the memory cells in the same row must also be erased. Row and column decoders decode incoming row and column addresses and provide the appropriate voltages to the control gate lines 22a and bit lines 16a, respectively. A sense amplifier senses the voltages or currents on the bit lines during read operations.
Those skilled in the art understand that the source and drain can be interchangeable, where the floating gate can extend partially over the source instead of the drain, as shown in FIG. 3. FIG. 4 best illustrates the corresponding memory cell architecture, including the memory cells 10, the source lines 14a, the bit lines 16a, and the control gate lines 22a. As is evident from the figures, memory cells 10 of the same row share the same source line 14a and the same control gate line 22a, while the drains of all cells of the same column are electrically connected to the same bit line 16a. The array design is optimized for digital applications, and permits individual programming of the selected cells, e.g., by applying 1.6 V and 7.6 V to the selected control gate line 22a and source line 14a, respectively, and grounding the selected bit line 16a. Disturbing the non-selected memory cell in the same pair is avoided by applying a voltage greater than 2 volts on the unselected bit lines 16a and grounding the remaining lines. The memory cells 10 cannot be erased individually because the process responsible for erasure (the Fowler-Nordheim tunneling of electrons from the floating gate 20 to the control gate 22) is only weakly affected by the drain voltage (i.e., the only voltage which may be different for two adjacent cells in the row direction sharing the same source line 14a).
Split gate memory cells having more than two gates are also known. For example, memory cells have source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a control gate 22 over a second portion of the channel region 18, a coupling gate 28 over the floating gate 20, and an erase gate 30 over the source region 14 are known, as shown in FIG. 5. It should be noted that coupling gates are sometimes referred to as control gates, but will only be referred to as coupling gates herein for clarity (so they may be distinguished from the control gates 22 used to control a portion of the channel region 18). Programming is shown by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is shown by electrons tunneling from the floating gate 20 to the erase gate 30 by the application of a high positive voltage on the erase gate 30.
The architecture for a four-gate memory cell array can be configured as shown in FIG. 6. In this embodiment, each horizontal control gate line 22a electrically connects together all the control gates 22 for that row of memory cells. Each horizontal coupling gate line 28a electrically connects together all the coupling gates 28 for that row of memory cells. Each horizontal source line 14a electrically connects together all the source regions 14 for two rows of memory cells that share the source regions 14. Each bit line 16a electrically connects together all the drain regions 16 for that column of memory cells. Each erase gate line 30a electrically connects together all the erase gates 30 for two rows of memory cells that share the erase gates 30. As with the previous architecture, individual memory cells can be independently programmed and read. However, there is no way to erase cells individually. Erasing is performed by placing a high positive voltage on the erase gate line 30a, which results in the simultaneous erasing of both rows of the memory cells that share the same erase gate line 30a. Exemplary operating voltages can include those in Table 1 below, where selected lines (Sel.) are those that include the targeted memory cell(s), and unselected lines (Unsel.) are the remaining lines not including eh targeted memory cell(s):
TABLE 1CG 22aBL 16aSL 14aCG 28aEG 30aSel.Unsel.Sel.Unsel.Sel.Unsel.Sel.Unsel.Sel.Unsel.Erase0 V0 V  0 V0 V0 V0 V  0 V  0 V11.5 V 0 VRead2.5 V  0 V0.8 V0 V0 V0 V2.5 V2.5 V  0 V0 VProgram1 V0 V  1 μA2.5 V  4.5 V  0.5 V  10.5 V 0/2.5 V  4.5 V0.5 V  
Split gate non-volatile memory cells having three conductive gates, and arrays of such cells, are also known. For example, U.S. Pat. No. 7,315,056 (“the '056 patent”) discloses an array of split gate non-volatile memory cells. The memory cell is shown in FIG. 7. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. A control gate 22 has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22b that extends up and over the floating gate 20. A program/erase gate 32 has a first portion 32a disposed over the source region 14 and is laterally adjacent to the floating gate 20, and a second portion 32b that extends up and over the floating gate 20.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the PE gate 32, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the PE gate 32 via Fowler-Nordheim tunneling.
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the source region 14 and a positive voltage on the PE gate 32. Electron current will flow from the drain 16 towards the source 14. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
The memory cell is read by placing positive read voltages on the drain 16 and control gate 22 (which turns on the channel region under the control gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the source 14), then the portion of the channel region under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
Exemplary operating voltages can be:
TABLE 2Control GateDrainPE GateSourceOperation(22)(16)(32)(14)Erase0010-12Volts0Program1-2Volts~1μA4-6Volts6-8 VoltsRead1.5-3.3Volts0.5-1.0Volts00
The architecture of the memory array is shown in FIG. 8. The memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end to end in mirror fashion, so that they are formed as pairs of memory cells each sharing a common source region 14, and each adjacent set of memory cell pairs sharing a common drain region 16. All the source regions 14 for any given row of memory cells are electrically connected together by a source line 14a. All the drain regions 16 for any given column of memory cells are electrically connected together by a bit line 16a. All the control gates 22 for any given row of memory cells are electrically connected together by a control gate line 22a. All the PE gates 32 for any given row of memory cells are electrically connected together by a PE gate line 32a. Therefore, while the memory cells can be individually programmed and read, memory cell erasure is performed by pairs of rows (each pair of rows of memory cells sharing PE gates 32 are erased together, by the application of a high voltage on the PE gate line 32a). If a particular memory cell is to be erased, all the memory cells in the two rows are also erased.
Recently, new applications for split gate non-volatile memory cells have been developed that requires each memory cell to be programmed to specific values (including analog values) for either multibit storage or analog signal storage. Programming can be performed by programming the memory cells using one or more short program voltage pulses, followed by a program verify operation to confirm the program state of the memory cell. If the cell is insufficiently programmed, one or more additional program pulses are applied. This continues until the program verify operation confirms the cell has achieved the desired program state.
However, if the program verify operation determines that a cell has been over-programmed (i.e., overshoot), there is no way to erase just that memory cell. The entire row, multiple rows, a block, or the entire array of memory cells would have be erased to address the over-programmed cell. Then, programming of all the erased cells would have to begin again from the beginning.
There is a need for a memory cell array that allows for compensation of an over-programmed memory cell without having to erase the surrounding memory cells.